It is known in the art to form EEPROM or EPROM semiconductor memory cell utilizing a single floating gate-type MOS transistor or utilizing serially connected such floating gate-type transistor and a MOS transistor which is used for cell selection. The floating gate-type transistor can store non-volatile information by injecting or removing electrons to the floating gate. A memory device can be constructed by arraying a plurality of such memory cells.
However, in this prior memory array structure using a single floating gate-type transistor or serially connected the floating gate-type transistor and MOS transistor, a large area of semiconductor body is required because each bit line contact is necessary for each cell due to an NOR logic structure, obstructing the improvement of integration of the memory.